*** NOTE ***
This is a copy of the original
webpage hosted on geocities.
I took the liberty of mirroring it here as geocities have a limit on the amount
of traffic generated by a webpage -it looks like there is a lot of interest for
webpal internals :-) The only think added by me is the pdf for the
CH9294G clock synthesizer
Some informations about the Webpal hardware
Schematics
This schematic has been took down by the actual board, with a bit of guesses and a lot of continuity checking.The Webpal has been built in two slighty different hardware versions.
The schematic below refers to the PWB-117A Ver.01, the only one I own. The other version uses a different Super-I/O controller, a FDC37C666 instead of the FDC37C665.
If you have access to the other version, please let me know the differences, so I can update the schematics to include both versions.
Download schematics (PDF, 4 pages, 1.59 MB): Webpal_1.0.pdf (in glorious b&w) or
Webpal_1.0c.pdf (in color).
Data sheets
Some pointers to the related data sheets:PS7500:
 |
CL-PS7500FE Advanced Data Book (PDF) [www.cirrus.com] 06/1997, V2.0 - 251 pages, 2.31 MB |
|
CL-PS7500FE Product Bulletin (PDF) [www.cirrus.com] 01/1999 - 4 pages, 64 KB |
|
CL-PS7500FE Development Kit Quick Start Guide (PDF) [www.cirrus.com] 04/1999, V1.0 - 6 pages, 136 KB |
|
CL-PS7500FE Development Kit Hardware User's Guide (PDF) [www.cirrus.com] 03/1999, V1.0 - 38 pages, 672 KB |
|
CL-PS7500FE Development Kit Schematics (PDF) [www.cirrus.com] 03/1999, V1.0 - 12 pages, 846 KB |
|
CL-PS7500FE Development Kit Software User's Guide (PDF) [www.cirrus.com] 03/1999, V1.0 - 18 pages, 174 KB |
|
CL-PS7500FE Development Kit Product Bulletin (PDF) [www.cirrus.com] 03/1999, DS7500DK-003 - 2 pages, 107 KB |
|
CS4330/31/33 8 Pin Stereo D/A Converter for Digital Audio (PDF) [www.cirrus.com] 05/1997 - 38 pages, 1.05 MB |
|
CH7001C VGA to NTSC/PAL Encoder (PDF) [www.chrontel.com] 18 pages, 108 KB More info and Application Notes on: http://www.chrontel.com/products/7001.htm Note: the webpal has a plain CH7001, not the C variant |
| CH9294G Clock synthesizer |
|
FDC37C665GT/666GT High Performance Multi-Mode Parallel Port Super I/O FD Controller (PDF) [www.smsc.com] 152 pages, 434 KB More info and Application notes on the SMSC site. |
|
8 Megabit CMOS 5.0 Volt only, Sector Erase Flash Memory (PDF) [edevice.fujitsu.com] or 8 Megabit CMOS 5.0 Volt only, Sector Erase Flash Memory (PDF) [www.amd.com] |
|
74HCT244 Octal 3-STATE Buffer (PDF) [www.fairchildsemi.com] 7 pages, 95 KB |
|
74HCT245 Octal 3-STATE Transceiver (PDF) [www.fairchildsemi.com] 7 pages, 103 KB |
|
AT89C52 - 8-bit Microcontroller with 8K Bytes Flash (PDF) [www.atmel.com] 24 pages, 355 KB More info on the Atmel site. |
Serial ports
The serial ports are tied to the J10 and J11 connectors, at TTL (well, CMOS actually) levels. To connect them to a real serial port, you need a level translator (e.g.: a MAX232).Some notes about the serial ports:
| The serial ports have the pull-ups on the output pins, while the inputs are left floating (seems a genuine mistake :-/). Anyway, connecting the level translators connects everything, so there's no problem here. |
| The 1st serial port is used to talk to the IR keyboard receiver/smart card controller. If you plan to use this port, you must cut JP2 and JP3 (on the solder side). Doing this will cause to lose the IR keyboard, of course. Failing to do this, you may experience all sorts of problems, because you are connecting together two outputs (the AT89C52 out and your MAX232 out). |
| The 2nd serial port has the RXD input tied to the "raw" infrared signal. To use the port as a serial console, be sure to cut JP1 (on the solder side), or the IR keyboard will no longer work. This modification has no drawbacks, because you still have the [decoded] signal available on the first serial port. |
Clocks
The clocks for the CPU are made using a Chrontel CH9294G clock syntesizer. The CH9294G provides three outputs: one is fixed at 14.31818 MHz and is used only to feed the CH7001 NTSL/PAL encoder, while the other two are frequency-programmable, strapping some pins to ground. The first programmable output is used to provide the CPU clock, while the other one feeds the video section (pixel clock). Both programming pins sets are hardwired to provide fixed frequencies (read on).Video clock
The video clock is set at 25.175 MHz and gives a plain vanilla 640*480 @ 60 Hz VGA video output (800 pixel total count =~ 31.5 KHz =~ 2*NTSC line).Tweaking the frequency pins of the CH9294G is possible to generate several higher frequencies, so should be possible obtain some more interesting resolutions (at least an 800*600 @ 75 Hz). The available frequencies are: 25.175, 28.32, 31.50, 36.00, 40.00, 44.90, 50.00, 65.00, 72.00, 75.00, 77.00, 80.00, 94.50, 110.00, 120.00 and 130.00 MHz.
The video section of the PS7500 accepts frequencies up to 120 MHz.
Changing the CH9294G pins is the simplest way to speed up the video circuitry, although isn't software controllable (unless you wire the frequency control pins to some port).
Here's a list of possible scan rates (not tried, just a guess):
Resolution | Vert.f (Hz) | Hor.f (KHz) | HTotal |Dot clock (MHz) -----------+-------------+-------------+--------+--------------- 640 x 480 | 60 NTSC | 31.5 | 800 | 25.175 LLLL (default) 640 x 480 | 50 PAL | ~31.25 | 806 | 25.175 LLLL (default) 720 x 480 | 60 NTSC | 31.5 | 900 | 28.32 720 x 576 | 50 PAL | ~31.25 | 906 | 28.32 640 x 480 | 72 | 36.5 | 864 | 31.5 HLHH 640 x 480 | 75 | 37.5 | 840 | 31.5 HLHH 640 x 480 | 85 | 31.5 | 832 | 36.00 LHHL 800 x 600 | 72 | 48 | 1040 | 50.00 LHLL 800 x 600 | 85 | 55.84 | 1160 | 65.00 HHLH 1024 x 768 | 72 | ???? | ???? | 80.00 HLHL 1024 x 768 | 85 | 70.24 | 1345 | 94.50 HHHHThe NTSC/PAL outputs are useful only if the video card outputs a signal with an horizontal frequency exactly doubled respect to the TV-horizontal frequency: 31.5 KHz for NTSC and 31.25KHz for PAL. Thus the upper TV-able resolution should be 720*480 @ 60 Hz or 720*576 @ 50 Hz.
The encoded video outputs are resampled by the CH7001, so the actual pixel rate (and thus the pixel "squareness") is just loosely related to the VGA dot clock (i.e.: do not assume an exact 2:1 ratio, see too the unused CH7001's pin UNDERSCAN).
The PS7500 supports a video PLL circuitry too, but no hardware has been fitted in the Webpal (nothing magic, just a 74AC04, a transistor and a couple of passives: see Appendix E in the PS7500 datasheet for the details).
CPU Clock
The PS7500 can operate with different frequencies for the CPU, the I/O and the MEMory. According to the datasheet, the maximum frequencies are: 40 MHz for CPU and 32 MHz for I/O and memory.Every input can be divided by 2 with an internal software selectable prescaler (at reset the divider is -of course- enabled), thus you can feed up to 80 MHz and 64 MHz, respectively.
The Webpal clock chip feeds to the PS7500 a neat 80 MHz, so the prescaler must be leaved on. Oddly enough, the Webpal hardware clocks everything at 80 (40) MHz, overclocking the I/O and memory sections by a neat 25%! Because of this, the divided signals outputs are shifted up accordingly:
CLK2 is 2.5 MHz
CLK8 is 10.0 MHz
CLK16 is 20.0 MHz
Audio DAC Clock
The clock for the audio DAC is provided by a separate oscillator, running at 22.1184 MHz. The frequency is wrong (should be 22.5792 or 11.2896 MHz, for a 44.100 KHz sampling rate, oversampled 512x and 256x, respectively), so the played audio is about a 2% slower :-(.NTSC/PAL Video encoder
The CH7001 video encoder provides the composite & S-Video outputs. The encoder expects, as input, an horizontal video frequency exactly doubled respect the output horizontal frequency (i.e.: input=31.5KHz, output 15.75KHz for NTSC). The vertical frequency must be the actual output frequency (60 Hz for NTSC).The video input signal is fully resampled and filtered by the encoder. The NTSC/PAL interlaced fields are made up by the encoder: as input you must provide a normal not-interlaced VGA field.
The IOP[0..7] pins of the PS7500 are connected to the encoder control lines. Every setting
controlled by these pins is related to the composite video & S-Video output only,
not the VGA out.
| IOP 0 | UP | The video output can be centered pressing several times (!) the button inputs connected to these four pins. |
| IOP 1 | DOWN | |
| IOP 2 | LEFT | |
| IOP 3 | RIGHT | |
| IOP 4 | NTSC/-PAL | This pin selects the encoding standard: a high level is NTSC, low is PAL. Is up to you provide appropriate frequencies to the video inputs (60 or 50 Hz). |
| IOP 5 | Power down | IOP5 controls the power down mode: pulling the pin low shuts down the encoder, sparing something around 330 mA (in other words, you cut the board power consumption by almost an half!). |
| IOP 6 | MS 1 | These two pins are used to select one of four possible anti-flicker vertical filter modes. |
| IOP 7 | MS 0 |
Note: the pin 37 (PD0) has a capacitor connected to Vcc, while according to the datasheet could be left open. Maybe the CH7001 and the CH7001C (the only one datasheet I'm been able to find around) are slighty different beasts, and here the pin 37 has a different function (i.e.: not power down).
DRAM SIMM
The RA11 address pin on the CLPS7500 is not wired to the RAM SIMM slot (is left floating on the SIMM side), so is possible to address up to 2^22 words/bank only (i.e. 16 Mbyte/bank).
Without modifications, you can fit a single bank (aka single sided) module with
2K refresh up to 16 MB or a double sided module up to 32 MB.
Wiring the missing address (see
http://www.luban.org/Webpal
for details & pictures) allows to use single sided SIMMs (w/4K refresh) up
to 64 MB, or 128 MB for the double sided version.
The PS7500 has two more (unused) DRAM chip selects, so is theorically
possible to fit a maximum of 256 MB (besides the missing socket).
IDE Slot
As you can see in the schematic, the D7 pin of the IDE connector is (wrongly) tied to the pin 11 of U2, so writing to the IDE interface causes a contention between the FDC37C665 and the buffer (which has the input open!). As workaround, lift up the pin 11 (if you hate having floating CMOS inputs around, feel free to provide a pullup/pulldown for both pins, 9 and 11 (and no, you cannot tie the pin directly to GND, because the buffer is bidirectional)).ISA Bus Slot
The ISA bus slot is decoded by the EASCS signal (physical address 0x08000000...0X0FFFFFFF).Some notes:
A lot of pins normally supposed to be signals coming from the motherboard and going to the card are left unconnected. This could cause several intermittent problems using cards with CMOS inputs. If you are experiencing this kind of problems, try to pull-up (or down, as appropriate, let's say 10K) the floating card's inputs. In detail, there's absolutely nothing connected to the DMA and to the MEMRD/MEMWR pins: forget to use any NIC card requiring DMA or memory mapped access.
The only interrupt pin connected to the slot is the IRQ3 (wired to the level-sensitive (active high) INT7 pin).
Some links...
| http://webpal.bigbrd.com/ by Bill Danielson Linux 2.4.0 port, loader, HW details, RS232 i/f, a lot more. |
| http://www.luban.org/Webpal by Vit_sfba Kb driver, RAM mods (w/pics), mtd driver, programmer board pics. |
| http://www.anycities.com/user/webpal/ by scratchy Patch for the IR keyboard key-rollover problem, KB mapping for X-Windows, GDB 5.0. |
| http://www.geocities.com/sparcusmaximus/ by SparcusMaximus Alternate Method of Programming the Webpal FLASH SIMM. |
| http://mtrob.fdns.net/~webpal/ HW info, emlilo (embedded linux loader). |
| http://manmicro.com/webpal/ by gr8_brit The Webpal original files. |
| http://www.linux-hacker.net/cgi-bin/UltraBoard/UltraBoard.pl ... The Linux Hacker Webpal Bulletin Board. |
| http://www.arm.linux.org.uk/ The ARM Linux Project. |
| http://www.bluewaternz.com/startoff/armlinux.htm Guide to building the ARM Linux Toolchain Kernel. |
Last update: 2002/01/06
